6 publications, most recent first.
TMLR (under review)
End-to-end framework for training FPGA-native neural networks using differentiable lookup tables instead of MAC operations. Provides modular PyTorch APIs, hardware-aware components, and automated RTL export with bit-accurate equivalence. Achieves 72.3% CIFAR-10 accuracy with <0.3M LUTs and <20 ns inference latency using LUT resources only.
AAAI 2026 Workshop on ML4Wireless
Hardware-efficient grayscale image codec based on trainable Boolean logic circuits. Learns lookup-table logic optimised for compression quality, energy, and latency. Outperforms traditional codecs while enabling deployment on edge and embedded hardware.
EdgeFM @ ICML / ICLR 2026 workshop track
First recurrent architecture based on differentiable logic gates. Extends Boolean neural computation to sequence modelling. Achieves 30.9% on WMT'14 En–De, approaching GRU performance with stable inference behaviour.
Preprint
Translates pushdown automata into trainable RNN architectures capable of exact arithmetic and bitwise computation. Identifies optimisation barriers and enables precise symbolic reasoning across multiple operations.
Deep Learning course project, ETH Zürich
Analysis of replay-based strategies for continual learning. Evaluates sensitivity-aware, weighted, and confidence-based sampling. Matches Goldilocks performance with improved robustness.
BSc Thesis, ETH Zürich
Transformer architecture for multivariate time-series classification using frequency enhancement, hierarchical attention, and adaptive masking. Evaluated on 18 benchmark datasets.