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GIC-DLC: Differentiable Logic Circuits for Hardware-Friendly Grayscale Image Compression
Simon Bührer, et al. · AAAI 2026 Workshop on ML4Wireless · January 2026
Abstract
Hardware-efficient grayscale image codec based on trainable Boolean logic circuits. Learns lookup-table logic optimised for compression quality, energy, and latency. Outperforms traditional codecs while enabling deployment on edge and embedded hardware.
Tags
- Learned Compression
- Boolean Logic
- Edge AI
- FPGA
- Energy-Efficient Systems