BitLogic: A Training Framework for Gradient-Based FPGA-Native Neural Networks
Simon Bührer, et al., TMLR, February 2026
Abstract
Gradient-based LUT- and logic-gate networks (LUTNet, LogicNets, DiffLogic, PolyLUT, NeuraLUT, and others) replace multiply-accumulate arithmetic with Boolean lookups, so one trained checkpoint runs on GPU, FPGA, and ASIC from a single code path. But every method ships its own pipeline, encoder, and wiring rules, so it is unclear which choices matter for accuracy and which for hardware cost. BitLogic is a unified framework that factors the field into a five-axis design space (encoder, connectivity, fan-in, node parameterization, head) and retrains every prior method under one protocol. Combining the per-axis winners yields a new best-of-space configuration that beats every retrained prior across MNIST, Fashion-MNIST, CIFAR-10, and CIFAR-100. On MNIST its two-layer network reaches ~126 MSamples/s on FPGA, ~15x the throughput of a bit-packed GPU path, at four-to-five orders of magnitude less energy.
Tags
- FPGA-Native ML
- Hardware-Aware Training
- Differentiable Logic
- RTL HDL Generation
- PyTorch
- Low-Latency Inference